Method for Planarization of Wafer and Method for Formation of Isolation Structure in Top Metal Layer

ABSTRACT

The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of prior application Ser. No.11/852,918, filed Sep. 10, 2007, the entire disclosure of which ishereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to a planarization process insemiconductor manufacturing, particularly to a method for planarizationof a wafer and a method for forming an isolation structure in a topmetal layer in Liquid Crystal on Silicon (LCOS) technique.

BACKGROUND OF THE INVENTION

With the rapid development of Ultra Large Scale Integration (ULSI)technique, integrated circuits (ICs) manufacturing techniques becomemore and more complex and precise. In order to improve an integrationdegree and reduce a manufacturing cost of a device, the Feature Size ofcomponents becomes smaller and smaller, and the number of components perunit area in a chip becomes higher and higher. Therefore, it isdifficult to meet the requirement for intense distribution of componentsby single-layer routing; multi-layer routing technique has been employedto utilize vertical space in a chip so as to further improve theintegration degree of device. However, the multi-layer metallizationresults in unevenness on the surface of the wafer and is severelydisadvantage for patterning. In order to implement a multi-layermetallization structure on a wafer with a large diameter, it is requiredto achieve a good overall flatness on each layer in the wafer, i.e., itis required a planarization process for a layer, such as conductor, ILD(Inter-Layer Dielectric), metal (e.g., W, Cu, Al) silicon oxide, andnitride etc., in the multi-layer interconnection structure.

Now, Chemical Mechanical Polishing (CMP) is a commonly planarizationmethod in wafer planarization process; however, latest investigationsshow that, the wafer surface flatness achieved by a conventional CMPcan't meet the requirement for some applications, such as an applicationin optical instruments, an application in image transmission or imageprocessing components and other products with a high requirement forsurface quality, and the yield of the products is very low, due to theextremely high requirement for wafer surface flatness.

For example, during the planarization for a top metal layer in LiquidCrystal on Silicon (LCOS) technique, the top metal layer 40 needs to bedivided into several small mirrors, as shown in FIG. 1A, in whichreference number 10 represents the ILD layer, reference number 20represents the intermediate metal layer, reference number 30 representsthe contact hole metal, and reference number 40 represents the top metallayer. Therefore, as shown in FIG. 1B, the top metal layer 40 and theILD layer 10 are etched to a certain depth to form a trench 50; then, asshown in FIG. 1C, an insulating oxide layer 60 is deposited over thetrench 50 and the top metal layer 40 to fill the trench 50; next, asshown in FIG. 1D, the insulating oxide layer 60 over the top metal layer40 is polished by a CMP process; finally, the entire insulating oxidelayer 60 on the top metal layer 40 is removed by a dry etching processto form a structure as shown in FIG. 1E. However, by means of amicroscopic surface analysis, it is found that the top metal layer 40formed by the above method has concentric ring recesses on the surface,as shown in FIG. 2, which causes the top metal layer 40 unable to beused as the mirror of LCOS.

Further investigation shows that the concentric ring recesses on the topmetal layer 40 is caused by concentric ring recesses on the surface ofthe polishing pad used in conventional CMP technique. For example, in apolishing pad structure described in China Patent ApplicationCN03140681, a surface of the polishing pad has grid, ring, or helixrecesses, as shown in FIG. 3. Since the surfaces of the polishing padshave recesses, the recesses similar to that in the polishing surfacewill be formed on the surface of the top metal layer 40 during CMPprocess, hence, degrading surface flatness of the top metal layer 40.

SUMMARY OF THE INVENTION

The main object of the present invention is to solve a problem of a poorwafer surface quality after a planarization process by CMP in the priorart.

To solve the above problem, the present invention provides a method forplanarization of a wafer having a surface layer with recesses,comprising:

forming an etching-resist layer on the surface layer to fill the recess,a thickness of the etching-resist layer in the recess being larger thanthat outside the recess;

etching the etching-resist layer and the surface layer; wherein, anetching speed of the surface layer is higher than that of theetching-resist layer, so that the portions outside the recess will notbe higher than the bottom of recess after the etching;

removing the etching-resist layer in the recess.

Wherein, if the etching-resist layer is a photoresist (PR) layer, themethod further comprises a process of patterning the PR layer after thePR layer is formed on the surface layer and before the etching-resistlayer and the surface layer are etched, so as to remove PR layer outsidethe recess. Or, the etching-resist layer may be a BARC (BottomAnti-Reflection Coat) layer.

Wherein, the etching-resist layer is formed by spin-coating process.

Wherein, the surface layer is made of one selected from a groupconsisting of silicon oxide, silicon nitride and aluminum (Al).

Wherein, the etching-resist layer and the surface layer are etched by adry etching process.

If a surface to be etched is silicon oxide or silicon nitride, the mainetching gas for etching the etching-resist layer and the surface layerincludes at least one of CxFy (1≦X≦9, 1≦Y≦9) and CHxFy (1≦X≦9, 1≦Y≦9).If the surface to be etched is Al, the etching gas for etching theetching-resist layer and the surface layer comprises an etching gascontaining halogen family elements.

Wherein, the etching-resist layer is removed by an asking process.

The present invention also provides a method for planarization of a topmetal layer on which an insulating oxide layer having recesses isformed, comprising:

forming an etching-resist layer over the insulating oxide layer to fillthe recess, the thickness of the etching-resist layer on the insulatingoxide layer in the recess being larger than that outside the recess;

etching the etching-resist layer and the insulating oxide layer,wherein, the etching speed of the insulating oxide layer is higher thanthat of the etching-resist layer, so that the insulating oxide layeroutside the recess in not higher than the bottom of the recess;

removing the etching-resist layer on the insulating oxide layer in therecess; and

etching the insulating oxide layer, till the top metal layer is exposedcompletely.

Wherein, if the etching-resist layer is a PR layer, the method furthercomprises a process of patterning the PR layer after the PR layer isformed on the insulating oxide layer and before the PR layer and theinsulating oxide layer are etched, so as to remove the PR layer outsidethe recess on the insulating oxide layer. The etching-resist layer maybe a BARC layer.

Wherein, the etching-resist layer is formed by a spin-coating process.

Wherein, the insulating oxide layer is made of one selected from a groupconsisting of silicon oxide, oxynitride, TEOS (tetraethylorthosilicate), and ONO (oxide-nitride-oxide).

The main etching gas for etching the etching-resist layer and theinsulating oxide layer includes at least one of CxFy (1≦X≦9, 1≦Y≦9) andCHxFy (1≦X≦9, 1≦Y≦9).

Wherein, the etching-resisting layer is removed by an ashing process.

Wherein, the top metal layer is an Al layer.

Wherein, the insulating oxide layer is etched till the top metal layeris exposed completely by a dry etching process.

The present invention also provides a method of isolating a top metallayer for a wafer having an ILD layer and the top metal layer on the ILDlayer, comprising:

etching the top metal layer and the ILD layer to a predetermined depth,to form a trench in the top metal layer and the ILD layer;

forming an insulating oxide layer over the top metal layer and thetrench to fill the trench so that the insulating oxide layer has arecess at a position corresponding to the trench;

forming an etching-resist layer over the insulating oxide layer to fillthe recess, the thickness of the etching-resist layer in the recessbeing larger than that outside the recess;

etching the etching-resist layer and the insulating oxide layer,wherein, the etching speed of the insulating oxide layer is higher thanthat of the etching-resist layer, so that the insulating oxide layeroutside the recess will not be higher than the bottom of the recess;

removing the etching-resist layer in the recess; and

etching the insulating oxide layer, till the top metal layer is exposedcompletely.

Wherein, if the etching-resist layer is a PR layer, the method furthercomprises a process of patterning the PR layer after the PR layer isformed over the insulating oxide layer and before the PR layer and theinsulating oxide layer are etched, so as to remove the PR layer outsidethe recess. Or, the etching-resist layer may be a BARC layer.

Wherein, the etching-resist layer is formed by a spin-coating process.

Wherein, the insulating oxide layer is made of one selected from a groupconsisting of silicon oxide, oxynitride, TEOS and ONO.

The etching gas for etching the etching-resist layer and the top metallayer includes at least one of CxFy (1≦X≦9, 1≦Y≦9) and CHxFy (1≦X≦9,1≦Y≦9).

Wherein, the etching-resist layer is removed by an ashing process.

Wherein, the top metal layer is an Al layer.

Wherein, the insulating oxide layer is etched till the top metal layeris exposed completely by a dry etching.

Wherein, the ILD layer is made of one selected from a group consistingof silicon oxide, oxynitride, TEOS, ONO and any other insulatingdielectric material with a higher K-value than silicon oxide.

The present invention has the following advantages over the prior art:

1. In the method for wafer planarization provided in the presentinvention, an etching-resist layer is formed over the recesses of wafer;then, the wafer and the etching-resist layer are etched; since theetching speed of the etching-resist layer is lower than that of thewafer surface, the etching-resist layer is removed when the wafersurface outside the recess is etched to flush to or lower than thebottom of the recess; and then the wafer surface is further etched tothe predetermined depth. The CMP process can be avoided by the abovemethod, and thereby concentric ring recesses on wafer surface resultedfrom CMP can be avoided. Furthermore, since an etching-resist layer isformed over the wafer to cover the recess, the recess is not etchedwhile the wafer surface outside the recess is etched. When the wafersurface outside the recess is etched to flush to or lower than thebottom of the recess, the etching-resist layer can be removed so thatthe entire wafer surface will be formed nearly in a plane. Moreover, thewafer surface flatness can be ensured after the wafer surface is furtheretched to a predetermined depth.

2. The method for top metal layer planarization in LCOS techniqueemploys an etching process for the top metal layer planarization andthereby avoids concentric ring recesses on the top metal layer caused byCMP. Therefore, a high-quality top metal layer can be obtained, and thedisplay quality of a LCOS LCD can be improved.

3. The present invention also provides a method for isolating a topmetal layer in LCOS, which can effectively isolate the top metal layerinto several mirrors. Since an etching process is used for planarizationof the top metal layer, the surfaces of the mirrors are highly flat.

4. The present invention employs a PR or BARC layer as theetching-resist layer; due to patterning capability of PR or thehalf-fluidity of BARC, the recesses described in the present inventioncan be filled completely, so that a flat wafer surface can be obtained.Therefore, the wafer surface still maintains flat after the dry etchingor wet etching process.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings. The drawings are not drawn to scale for the purpose ofillustrating the spirit of the present invention. In the drawings, thethicknesses of layers and the area of regions are amplified forclearness.

FIG. 1A-1E are schematic cross-section diagrams of a wafer during aplanarization process for a top metal layer in LCOS in the prior art;

FIG. 2 is a schematic diagram of the surface of the top metal layerafter the planarization process in LCOS in the prior art;

FIG. 3 is a schematic diagram of a surface of the polishing pad used inCMP in the prior art;

FIG. 4A-4D are schematic cross-section diagrams of the wafer during aplanarization process according to the method provided in the presentinvention;

FIG. 5A-5D are schematic cross-section diagrams of the wafer during theplanarization process for the top metal layer in LCOS according to thepresent invention;

FIG. 6A-6G are schematic cross-section diagrams showing a method forisolating the top metal layer in LOCS according to an embodiment in theinvention in the case that the etching-resist layer is a PR layer; and

FIG. 7 is a SEM (Scanning Electron Microscope) image of the insulatingoxide layer formed on the top metal layer with recesses according to thethird embodiment in the present invention;

FIG. 8 is a SEM image of the wafer after the etching-resist layer isremoved in the third embodiment in the present invention;

FIG. 9A-9G are structural diagrams showing the process according to thefourth embodiment in the present invention;

FIG. 10 is a SEM image of the wafer after the recess on the insulatingoxide is filled with the etching-resist layer in the fourth embodiment;

FIG. 11 is a SEM image of the wafer showing an isolation structure forthe top metal layer according to the fourth embodiment in the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings.

Embodiment 1

The present invention provides a method for planarization of a waferhaving a surface layer with recesses, comprising: forming anetching-resist layer on the surface layer to fill the recess and thethickness of the etching-resist layer in the recess is larger than thatoutside the recess; etching the etching-resist layer and the surfacelayer; wherein, the etching speed of the surface layer is higher thanthat of the etching-resist layer, so that the portions of the surfacelayer outside the recess will not be higher than the bottom of recessafter etching; and removing the etching-resist layer.

As shown in FIG. 4A, a wafer having a semiconductor substrate 100 isprovided; the semiconductor substrate 100 may be applied tosemiconductor manufacturing processes, and may have devices and circuitsformed therein. Due to the fact that different devices and circuits maybe contained in different structures depending on the specificmanufacturing processes, the internal structure of the semiconductorsubstrate 100 is not shown in the drawings of the present invention.However, it shall not be deemed to constitute any limitation to theapplicability and scope of the present invention. The semiconductorsubstrate 100 has a surface layer 110 with a recess 120; the surfacelayer 110 may be made of a material such as semiconductor, ILD, metal(e.g., W, Cu, Al), silicon oxides, or nitrides, which need to besubjected to a surface planarization process.

As shown in FIG. 4B, an etching-resist layer 130 is formed over thesurface layer 110 to fill the recess 120, resulting in a plane structurewithout recesses. In order to make the thickness of an etching-resistlayer filled in the recess 120 is larger than that outside the recess(i.e., the regions other than the recess on the surface layer 110) onsurface layer 110, the present invention employs a PR or BARC layer withgood fluidity as the etching-resist layer. A thickness of theetching-resist layer 130 varies along the unevenness of the surfacelayer when it is filled into the recess 120 due to its good fluidity;therefore, the thickness of the etching-resist layer 130 in the recessis larger than that outside the recess. As a result, a differencebetween the heights of portions in and outside the recess is reducedgreatly or is even eliminated and hence forming a flat surface.

The PR coat is formed by a conventional spin-coating process. A PR layeris coated over the entire surface layer 110; due to the fluidity of PRand the inherent advantages of spin-coating, the resulted PR layer canfill the recess 120; then, a photo-mask is applied on the PR layer toform a PR pattern; then, only a portion of the PR layer corresponding tothe recess is left after exposure and development.

If the etching-resist layer is a BARC layer, it can also be formed bythe spin-coating process, so as to fill the entire recess 120 and coverthe surface layer 110, as shown in FIG. 4B.

Next, as shown in FIG. 4C, the surface layer 110 and the etching-resistlayer 130 are etched, till the surface layer 110 is flush to the bottomof the recess 120 or slightly lower than the bottom of the recess 120;during the etching process, a proper etching gas components should beselected to ensure that the etching speed of the surface layer is higherthan that of the etching-resist layer, so that the entire surface layermaintains flat after the etching process for surface layer 110 andetching-resist layer 130, without introducing new recesses. Preferably,the surface layer 110 is flush to the bottom of the recess 120 after theetching process for surface layer 110 and the etching-resist layer 130.

In the present invention, if the etching-resist layer 130 is a PR layer,the consumption of PR during the etching process can be neglected, sincethe thickness of PR is adjustable and the conventional etching gases haslittle etching effect on the PR. Therefore, a proper etching gas can beselected in accordance with the material of surface layer 110. Dependingon the material of the surface layer, a conventional etching gas is alsopossible. Therefore, the description thereof is omitted here. Forexample, if the surface layer 110 is a silicon oxide layer, then CF4 orthe like can be used as the etching gas.

If the etching-resist layer 130 is a BARC layer, a proper etching gasshall be chosen to ensure that the etching speed of the BARC layer islower than that of the surface layer. However, a conventional etchinggas is also possible. For example, if the surface layer is a siliconoxide layer, an etching gas including at least one of CxFy (1≦X≦9,1≦Y≦9) and CHxFy (1≦X≦9, 1≦Y≦9) can be used.

Finally, as shown in FIG. 4D, the etching-resist layer 130 is removed.If the etching-resist layer 130 is a PR layer, the etching-resist layercan be removed by a conventional process for removing PR, such as anashing process. If the etching-resist layer 130 is a BARC layer, theetching-resist layer 130 can also be removed by a conventional process,such as an ashing process.

Embodiment 2

The present invention also provides a method for planarization of a topmetal layer in LCOS, wherein the top metal layer is contained in a waferand includes a trench and an insulating oxide layer including a recessformed over the trench and the top metal layer, a position of the recessin the insulating oxide layer corresponding to the trench; the methodcomprises the following steps: forming an etching-resist layer over theinsulating oxide layer to fill the recess, the thickness of theetching-resist layer in the recess being larger than that outside therecess; etching the etching-resist layer and the insulating oxide layer,wherein the etching speed of the insulating oxide layer is higher thanthat of the etching-resist layer, so that the insulating oxide layeroutside the recess will not be higher than the bottom of the recess;removing the etching-resist layer; and etching the insulating oxidelayer till the top metal layer is exposed completely.

As shown in FIG. 5A, a wafer including devices and circuits (not shown)is provided for the process in LCOS fabrication, which has at least twometal wiring layers. A sectional view of the wafer is shown in FIG. 5A,in which reference number 510 represents an ILD layer. A top metal layer540 is formed on the ILD layer 510. A trench 550 extending through thetop metal layer 540 and to a certain depth in the ILD layer 510 isformed and an insulating oxide layer 560 with recess 580 is filled overthe trench 550 and the top metal layer 540, the position of the recess580 corresponding to the trench 550.

The top metal layer 540 may be made of Al, copper (Cu), or silver (Ag);and Al is preferable for the top metal layer due to a higherreflectivity and a lower price.

The ILD layer 510 and insulating oxide layer 560 are made of oneselected from a group consisting of silicon oxide, oxynitride, TEOS,ONO, and any other high K-value insulating material with dielectricconstant higher than that of silicon oxide.

As shown in FIG. 5B, an etching-resist layer 570 is formed over aninsulating oxide layer 560 to fill the recess 580, and the thickness ofthe etching-resist layer 570 in the recess is larger than that outsidethe recess; preferably, the etching-resist layer 570 forms a planestructure without recess. In the present invention, a PR or BARC layeris used as the etching-resist layer. A thickness of the etching-resistlayer 570 varies along with the unevenness of the surface layer when theetching-resist is filled into the recess 580 due to its good fluidity;therefore, a thickness of the etching-resist layer 570 in the recessregion is larger than that outside the recess. As a result, thedifference between the heights of the etching-resist layer 570 in andoutside the recess is reduced greatly or is even eliminated and henceforming a flat surface. The formation of the BARC and PR layer isdescribed in the first embodiment.

Next, as shown in FIG. 5C, the insulating oxide layer 560 and theetching-resist layer 570 are etched, till the insulating oxide layer 560is flush to the bottom of recess 580, or slightly lower than the bottomof recess 580.

In the present invention, if the etching-resist layer 570 is a PR layer,a conventional etching gas well-known to those skilled in the art can beused to etch the insulating oxide layer 560 by a dry etching. If theetching-resist layer 570 is a BARC layer, an etching gas including atleast one of CxFy (1≦X≦9, 1≦Y≦9), CHxFy (1≦X≦9, 1≦Y≦9), Ar, and O₂ canbe used, and the mixing ratio of the etching gases can be adjusted, sothat the etching rate of the insulating oxide layer 560 is higher thanthat of the etching-resist layer 570. The insulating oxide layer 560 isetched, till it is flush to or slightly lower than the bottom of therecess 580. Preferably, the insulating oxide layer 560 is flush to thebottom of the recess 580.

Finally, as shown in FIG. 5D, the etching-resist layer 570 is removed.The process for removing the etching-resist layer is described in thefirst embodiment. After the etching-resist layer 570 is removed, theinsulating oxide layer 560 is further etched, till the top metal layer540 is exposed completely.

The top metal layer 540 mentioned above has a flat surface after theplanarization. Therefore, the concentric ring recesses on the top metallayer 540, resulted from etching the insulating oxide layer 560 afterthe CMP process for polishing the insulating oxide layer 560 in theprior art, can be avoided.

Embodiment 3

The present invention also provides a method for planarization of a topmetal layer in LCOS, wherein a wafer having an ILD layer and a top metallayer formed over the ILD layer is provided, the method comprising thefollowing steps: etching the top metal layer and the ILD layer to apredetermined depth, to form a trench in the top metal layer and the ILDlayer; forming an insulating oxide layer over the top metal layer andthe trench so as to fill the trench, the insulating oxide layer having arecess at a position corresponding to the trench; forming anetching-resist layer over the insulating oxide layer to fill the recess,and a thickness of the etching-resist layer in the recess is larger thanthat outside the recess; etching the etching-resist layer and theinsulating oxide layer, the etching speed of the insulating oxide layerbeing higher than that of the etching-resist layer, so that theinsulating oxide layer outside the recess will not be higher than thebottom of the recess; removing the etching-resist layer; and etching theinsulating oxide layer till the top metal layer is exposed completely.

As shown in FIG. 6A, a wafer including devices and circuits (not shown)is provided for the process in LCOS fabrication, which has at least twometal wiring layers. A sectional view of the wafer is shown in FIG. 6Ain which reference number 210 represents an ILD layer. A top metal layer240 is formed on the ILD layer 210 and the ILD layer 210 has anintermediate metal layer 220 and a metal contact hole 230 connecting theintermediate metal layer 220 with the top metal layer 240. In LCOS, thetop metal layer 240 is used as a mirror, which reflects optical signalsthrough the liquid crystal to the screen. In post-process for LCOS, atop metal layer 240 needs to be isolated into several small mirrors,each of which acts as a pixel unit. A number of pixel units present acomplete image on the screen.

In the present invention, the top metal layer 240 can be made of one ofAl, Cu and Ag. Al is preferred for the top metal layer due to its higherreflectivity and lower price.

The ILD layer 210 is made of one of silicon oxide, oxynitride, TEOS,ONO, and any other high K-value insulating material with dielectricconstant higher than that of silicon oxide. The intermediate metal layer220 may comprise any conventional inter-layer metal, such as Al, Cu orthe like; the metal contact hole 230 may be made of one of Cu, Al, W, orany other metal suitable for the contact hole.

As shown in FIG. 6B, the top metal layer 240 and ILD layer 210 areetched to a certain depth to form a trench 250. Preferably, the topmetal layer 240 and ILD layer 210 are etched by a dry etching process.

Next, as shown in FIG. 6C, an insulating oxide layer 260 is formed overthe trench 250 and the top metal layer 240, so as to fill the trench250. The insulating oxide layer 260 is made of an insulating material,such as silicon oxide, oxynitride, TEOS, or ONO or the like. Theinsulating oxide layer 260 is formed by, for example, a CVD (chemicalvapor deposition) process, preferably a PECVD (plasma enhanced chemicalvapor deposition) process. The CVD process is well-known to thoseskilled in the art, and therefore a description thereof is omitted.After the insulating oxide layer 260 is formed over the trench 250 andthe top metal layer 240 by a CVD process, a recess 280 is formed on theinsulating oxide layer 260 at a position corresponding to the trench250. FIG. 7 shows a SEM image of the recess 280 formed on the insulatingoxide layer 260 at a position corresponding to the trench 250 in thefabrication of the LCOS.

As shown in FIG. 6D, an etching-resist layer 270 is formed on theinsulating oxide layer 260 to fill the recess 280, so that a thicknessof the etching-resist layer 270 in the recess is larger than thatoutside the recess; preferably, the etching-resist layer 270 forms aplane structure without recesses. In order to fill the entire recess 280completely with the etching-resist, a PR with fluidity is used as theetching-resist layer in this embodiment. The PR layer is coated over theinsulating oxide layer 260 by a conventional spin-coating process; dueto the fluidity of PR and the inherent advantages of the spin-coatingprocess, a thickness of the etching-resist layer 270 varies along withthe unevenness of the surface layer when the etching-resist is filledinto the recess 280. Therefore, a thickness of the etching-resist layer270 in the recess is larger than that outside the recess. As the result,the difference between the heights of the etching-resist layer in andoutside the recess is reduced greatly or is even eliminated and henceforming a flat surface. Next, a photo-mask is applied on the PR layer toform a PR pattern, and only the PR in the recess 280 is left by exposureand development, hence forming the structure shown in FIG. 6D.

Next, as shown in FIG. 6E, the insulating oxide layer 260 andetching-resist layer 270 are etched. Since the etching-resist layer 270includes PR and the etching effect of any conventional etching gas to PRcan be neglected, an conventional etching process effective to theinsulating oxide layer 260 can be selected to etch the insulating oxidelayer 260, till the insulating oxide layer 260 is flush to or slightlylower than the bottom of the recess 280.

Preferably, the insulating oxide layer 260 is etched by a dry etchingprocess in this embodiment. As shown in FIG. 6F, the etching-resistlayer 270 is removed by a conventional ashing process.

Finally, as shown in FIG. 6G, the insulating oxide layer 260 is furtheretched, till the top metal layer 240 is exposed completely. The processfor etching the insulating oxide layer 260 is identical to thatdescribed in other steps of the embodiment. FIG. 8 shows a SEM image ofthe isolation structure in the top metal layer formed by the abovemethod. The top metal layer 240 has a flat surface structure. Since theisolation structure of top metal layer 240 formed by a embodiment of theinvention can avoid concentric ring recesses on the top metal layer 240generated during planarization of the insulating oxide layer 260 by aCMP process in the prior art, the top metal layer formed in theembodiment has a flat surface suitable for optical applications.

Embodiment 4

As shown in FIG. 9A, a wafer including devices and circuits (not shown)is provided for the process in LCOS fabrication, which has at least twometal wiring layers. A sectional view of a part of the wafer is shown inFIG. 9A in which reference number 310 represents an ILD layer. A topmetal layer 340 is formed on a surface of the ILD layer 310. The ILDlayer 310 has an intermediate metal layer 320 and a metal contact hole330 connecting the intermediate metal layer 320 and the top metal layer340. In LCOS, the top metal layer 340 is used as a mirror, whichreflects optical signals to a screen through a liquid crystal. Inpost-processes for LCOS, a top metal layer 340 needs to be isolated intoseveral small mirrors, each of which acts as a pixel unit. A number ofpixel units present a complete image on the screen.

In the present invention, the top metal layer 340 can be made of one ofAl, Cu, or Ag. Al is preferred for the top metal layer due to its higherreflectivity and lower price.

The ILD layer 310 is made of one of silicon oxide, oxynitride, TEOS,ONO, or any other high K-value insulating material with dielectricconstant higher than that of silicon oxide. The intermediate metal layer320 may be made of any conventional inter-layer metal, such as Al, Cu orthe like. The metal contact hole 330 may be made of one of Cu, Al, W, orany other metal suitable for the contact hole.

As shown in FIG. 9B, the top metal layer 340 and ILD layer 310 areetched to a certain depth to form trench 350. Wherein, the etchingprocess for the top metal layer 340 and ILD layer 310 is identical tothe etching process for the top metal layer 240 and the ILD layer 210 inthe third embodiment.

Next, as shown in FIG. 9C, an insulating oxide layer 360 is formed overthe trench 350 and the top metal layer 340, so as to fill the trench350. The insulating oxide layer 360 is made of an insulating material,such as silicon oxide, oxynitride, TEOS, or ONO or the like. Theinsulating oxide layer 360 is formed by, for example, a CVD process,preferably a PECVD process. After the insulating oxide layer 360 isformed over the trench 350 and the top metal layer 340 by a CVD process,a recess 380 is formed on the insulating oxide layer 360 at a positioncorresponding to the trench 350.

As shown in FIG. 9D, an etching-resist layer 370 is formed over theinsulating oxide layer 360 to fill the recess 380, so that a thicknessof the etching-resist layer 370 in the recess is larger than thatoutside the recess. Preferably, the etching-resist layer 370 forms aplane structure without recesses. The etching-resist layer 370 is a BARClayer. The BARC layer is coated by a conventional spin-coating process.A thickness of the etching-resist layer 370 varies along with theunevenness of the surface when the etching-resist is filled into therecess 380. Therefore, a thickness of the etching-resist layer 370 inthe recess is larger than that outside the recess. As a result, thedifference between the heights of portions in and outside the recess isreduced greatly or is even eliminated and hence forming a flat surface.FIG. 10 is a SEM image showing the recess 380 filled with BARC. The ILDlayer 310, top metal layer 340 and insulating oxide layer 360 in FIG. 10correspond to the ILD layer 310, top metal layer 340 and insulatingoxide layer 360 in FIG. 9.

Next, as shown in FIG. 9E, the insulating oxide layer 360 andetching-resist layer 370 are etched, preferably by a conventional dryetching process using CxFy (1≦X≦9, 1≦Y≦9), Ar, or O2 as an etching gasin the embodiment. In addition, the mix ratio of the etching gases isadjusted, so that the etching speed of insulating oxide layer 360 ishigher than that of etching-resist layer 370, till the insulating oxidelayer 360 is flush to or slightly lower than the bottom of the recess380, preferably, the insulating oxide layer 360 is flush to the bottomof the recess 380 after the etching process.

As shown in FIG. 9F, the etching-resist layer 370 is removed. Since theetching-resist layer 370 is a BARC layer, it can be removed by aconventional process, such as ashing.

Finally, as shown in FIG. 9G, the insulating oxide layer 360 is furtheretched, till the top metal layer 340 is exposed completely. The etchingprocess for the insulating oxide layer 360 is identical to the etchingprocess for the etching-resist layer described in other steps of theembodiment. FIG. 12 shows a SEM image of the isolation structure in thetop metal layer formed with above method. As shown in FIG. 12, the topmetal layer 340 has a flat surface. Since the isolation structure of thetop metal layer 340 formed by an embodiment of the invention can avoidconcentric ring recesses on the top metal layer 340 generated duringplanarization of the insulating oxide layer 360 by a CMP process in theprior art, the top metal layer formed in the embodiment has a flatsurface suitable for optical applications.

While the present invention has been illustrated and described withreference to some preferred embodiments, the present invention is notlimited to these. Those skilled in the art should recognize that variousvariations and modifications can be made without departing from thespirit and scope of the present invention as defined by the accompanyingclaims.

1. A method for planarization of a wafer having a surface layer with arecess, comprising: forming an etching-resist layer over the surfacelayer, a thickness of the etching-resist layer in the recess beinglarger than that outside the recess; etching the etching-resist layerand the surface layer; wherein, an etching speed of the surface layer ishigher than that of the etching-resist layer, so that the surface layeroutside the recess will not be higher than the bottom of recess;removing the etching-resist layer in the recess.
 2. The method accordingto claim 1, wherein the etching-resist layer is a PR (photoresist)layer.
 3. The method according to claim 2, wherein the method furthercomprises a process of patterning the etching-resist layer after theetching-resist layer is formed on the surface layer and before theetching-resist layer and the surface layer are etched, so as to removethe etching-resist layer outside the recess.
 4. The method according toclaim 1, wherein the etching-resist layer is a BARC (BottomAnti-Reflection Coat) layer.
 5. The method according to claim 1, whereinthe etching-resist layer is formed by a spin-coating process.
 6. Themethod according to claim 1, wherein the surface layer is made of oneselected from a group consisting of silicon oxide, silicon nitride andaluminum (Al).
 7. The method according to claims 6, wherein theetching-resist layer and the surface layer are etched by a dry etchingprocess.
 8. The method according to claim 6, wherein a main etching gasfor etching the etching-resist layer and the surface layer comprises atleast one of CxFy and CHxFy, wherein 1≦X≦9, 1≦Y≦9, in the case that thesurface layer is a silicon oxide or a silicon nitride layer.
 9. Themethod according to claims 6, wherein the etching gas for etching theetching-resist layer and the surface layer comprises an etching gascontaining halogen family elements, in the case that the surface layeris an Al layer.
 10. The method according to claim 1, wherein theetching-resist layer is removed by an ashing process.